Device performance of transistors can be significantly enhanced if devices are built on strained silicon-on-insulator (SSOI) wafers. The enhancements come from enhanced carrier transport in the strained Si, reduced junction capacitances due to a limited silicon volume, and a reduced leakage current due to isolation by the insulating layer. In general, past methods for producing strained silicon-on-insulator (SSOI) wafers have involved (1) epitaxial growth of a strained silicon layer on a strain-induced seed layer; and (2) transfer of the strained layer and the strain-induced seed layer to an insulator substrate. This transfer step involves implantation of hydrogen ions to a depth beyond the strained layer, bonding the surface of the strained layer to an insulator surface; annealing the bonded structure to generate hydrogen-induced cracks at a depth which is close to the projected range of hydrogen ions; and separation of the structure along the region of microcracks. An example of this transfer method can be found in U.S. Pat. No. 6,992,025 to Maa et al. entitled “Strained Silicon on Insulator from Film Transfer and Relaxation by Hydrogen Implantation”. According to the '025 patent, a SiGe layer is deposited on the silicon substrate. The SiGe layer is relaxed by implanting relaxing ions through the SiGe layer into the Si substrate. After polishing, a thin Si layer is deposited onto the SiGe layer. There is a difference in lattice constants between the Si and the SiGe layers. The SiGe layer is used as a strain-induced seed layer to generate strains in the Si layer. Afterward, the Si/SiGe multilayer film is transferred by implantation of ions to a region below the Si/SiGe interface. This method requires that strained Si layer to be directly bombarded by the splitting ions, which results in a strain relaxation in the strained layer. Also the ion bombardments can significantly degrade the crystalline quality.
Another method for preparing an SSOI wafer is described in U.S. Pat. No. 6,603,156 to Rim, entitled “Strained Silicon on Insulator Structures”. According to the '156 patent, a multilayer structure of strained-Si/SiGe/Si is bonded to a substrate so that an insulating layer directly contacts the strained Si layer. Afterward, the SiGe layer is removed. The SiGe layer is removed by a selective chemical etching that preferentially etches the SiGe substrates. This method, however, is unsuitable for the preparation of large SSOI wafers requiring ultrathin and smooth strained Si layers.
Another method to preparing an SSOI wafer is described in U.S. Pat. No. 6,911,379 to Yeo et al. entitled “Method of Forming Strained Silicon on Insulator Substrate”. According to the '379 patent, the layer transfer of a strained layer to an insulator layer is realized by hydrogen ion implantation, wafer bonding and annealing. Before bonding, the insulating layer is deposited with a high stress film. The high stress film can help retain the strain of the transferred strained layer. This method, however, has disadvantages of strain relaxation and radiation damage caused by hydrogen ion implantation.
In general, for the above methods, splitting is realized by a traditional ion-implantation-based ion-cutting technique. This technique is described in U.S. Pat. No. 5,374,564 to Bruel, entitled “Process for the Production of Thin Semiconductor Material Films”. According to the '564 patent, hydrogen ions are implanted into a semiconductor substrate to induce cracking at a depth close to the projected range of H ions. The networking of microcracks finally results in the cleavage of the top semiconductor layer. This method has disadvantages of the requirement of a high fluence of hydrogen (above 5×1016 cm−2), the difficulty in transferring an ultra thin (<0.1 micron) layer, and the low crystalline quality of the transferred layer due to surface damage induced by the hydrogen ion implantation. When this method is used for a layer transfer of a stained Si layer, the implantation-induced strain relaxation represents another major issue.
In view of the drawbacks mentioned above with prior art methods of manufacturing SSOI wafers, there is a need to develop a new method in which a smooth cleavage can be realized without degrading the quality of the strained Si layer. Also the new method should be low cost. For example, the steps required for surface polishing and cleaning need to be minimized.